Functional testing of microprocessor-based units or boards is employed to locate faults or malfunctions which affect operation of semiconductor memories or chips. It has been recognized by those skilled in the art that a functional test will locate all the possible faults that may occur performs on the order of 2.sup.N accesses, where N is the number of addressable locations or cells within the memory, and therefore is impractical because of the complexity and time involved. Accordingly, as a practical matter, any feasible test procedure must be concerned only with those faults that are most likely to occur, such as, for example, stuck data cells, defective decoders, defective address or data registers, and faults between address and data lines.
One test capable of detecting the most common faults by performing a number of operations at each memory address is the so-called march test that sequences or marches up and down through a range of addresses between given lower and upper bounds, performing the same operations, e.g., write and read, at each address. Early prior art investigators proposed rather lengthy and rigid march test, such a up to 30N tests, either writing the same bit into all cells, or writing a fixed pattern of "ones" and "zeros." While such tests located faults with a high degree of accuracy, they were very time consuming. In U.S. Pat. No. 4,715,034, David M. Jacobson taught a fast memory test algorithm which required only 5N operations using pseudorandom data to detect most of the common faults, and exploited the fact that the probability of failing to detect a fault was extremely small.
Where memory circuits are random-access memories (RAMs) of microprocessor-based systems, microprocessor emulation devices have been used for many years for performing functional tests in the process of design, production, or service testing and repair. An example of such a system is described in U.S. Pat. No. 4,455,654 to K. S. Bhaskar et al. The performance of memory testing in such microprocessor-based systems, or units under test (UUT's) is typically limited by accuracy-versus-speed tradeoffs which are dependent upon the emulator architecture and the test algorithm used. The microprocessor emulation device, which contains a microprocessor of the same type as that of the UUT, connects directly or via an interface pod to the UUT's bus structure, for example, by connecting directly into the UUT's microprocessor socket. All testing performed by such emulation devices has heretofore been carried out in a bus-access mode wherein the emulation device makes single cycles of bus accesses and acts on each one before making another. That is, the emulation device knows which addresses to write and read, and for one bus cycle makes a connection to the UUT's bus with a specific address preloaded on it so that the UUT's memory either will be written at that address, or will give the value of the data stored at that address, depending on whether a write or a read command is given. Then the emulation device switches over to its internal circuitry to generate another write command with a new address, or deal with information read from the UUT's memory. With the aforementioned Jacobson algorithm, a new pseudorandom number is calculated for each address. Since the use of single cycles of bus accesses has been the basis for prior art RAM testing, whether resident in a mainframe or a pod, increases in memory size translate directly into more cycles of bus accesses and a corresponding increase in testing time. Thus, even with faster test algorithms such as Jacobson's 5N probabilistic functional RAM test procedure, the trend toward providing increased RAM space presents a problem in terms of the time it takes to test a UUT.